EDA Front End Solutions: Teklatech and PinDown by Verifyter


At QLS we offer unique EDA solutions significantly reduce design verification times. Our EDA Front End tools include simulation acceleration, automated debug and design checking solutions.  Please see our specific solutions below.



Teklatech - resolves the challenges of next generation technologies that 16nm, 10nm and 7nm place on timing closure and die size.  Using Teklatech saves valuable routing resources thereby enabling your current design tools (Synopsys ICC and Cadence Innovus) to close timing that much faster or shrink your die size.  Also optimize your SOC Power Integrity through Teklatech's unique algorithm:  http://teklatech.com/web2/ Please contact us for more information on Teklatech.

  • PinDown reduces verification debug times by up to 400% or more by automating the manual debug triage process.  PinDown fits seamlessly into existing current test benches without requiring and changes.  If your design teams are spending days trying to debug test bench failures, we encourage you to schedule a time to learn more about PinDown.  verifyter.com